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? semiconductor components industries, llc, 2014 december, 2014 ? rev. 6 1 publication order number: ncp308/d ncp308, ncv308 low quiescent current, programmable delay time, supervisory circuit the ncp308 series is one of the on semiconductor supervisory circuit ic families. it is optimized to monitor system voltages from 0.405 v to 5.5 v, asserting an active low open?drain reset output, together with manual reset (mr ) input. the part comes with both fixed and externally adjustable versions. features ? wide supply voltage range 1.6 to 5.5 v ? very low quiescent current 1.6 a ? fixed threshold voltage versions for standard voltage rails including 0.9 v, 1.2 v, 1.25 v, 1.5 v, 1.8 v, 1.9 v, 2.5 v, 2.8 v, 3.0 v, 3.3 v, 5.0 v ? adjustable version with low threshold voltage 0.405 v (min) ? high threshold voltage accuracy: 0.31% typ ? support manual reset input ( mr ) ? open?drain reset output (push?pull output upon request) ? flexible delay time programmability: 1.25 ms to 10 s ? temperature range: ?40 c to +125 c ? small tsop?6 and wdfn6 2 x 2 mm, pb?free packages ? ncv prefix for automotive and other applications requiring unique site and control change requirements; aec?q100 qualified and ppap capable ? these are pb?free devices typical applications ? dsp or microcontroller applications ? notebook/desktop computers ? pdas/hand?held products ? portable/battery?powered products ? fpga/asic applications mr vdd (optional) rpullup sense ct gnd vdd ct r1 r2 figure 1. typical application circuit for adjustable versions 1 nf (optional) ncp308xxadj dsp/ reset figure 2. typical application circuit for fixed versions processor vin mr reset mr vdd (optional) rpullup sense ct gnd vdd ct dsp/ reset processor vin mr reset see detailed ordering and shipping information in the ordering information section on page 9 of this data sheet. ordering information tsop?6 case 318g www. onsemi.com marking diagrams (note: microdot may be in either location) 1 xxx, xx= specific device code a =assembly location y = year w = work week m = date code = pb?free package xxxayw 1 wdfn6 case 511br xx m 1
ncp308, ncv308 www. onsemi.com 2 vdd sense ? vref + control logic and timer ct gnd 90k vdd adjustable versions ncp308snadj/ncp308mtadj sense vdd ? vref + ct control logic and timer gnd 90k vdd ncp308snxxx/ncp308mtxxx fixed versions r1 r2 figure 3. functional block diagrams of adjustable and fixed versions mr reset mr rese t figure 4. pin connections diagram (top view) 1 2 3 6 5 4 gnd vdd sense ct reset mr 1 2 3 6 5 4 vdd sense ct reset mr gnd table 1. pin out description name pin number description tsop?6 wdfn6 vdd 6 1 supply voltage . a 0.1uf ceramic capacitor placed close to this pin is helpful for transient and parasitic. sense 5 2 sense input , this is the voltage to be monitored. if the voltage at this terminal drops below the threshold voltage v it , then reset is asserted. sense does not necessary monitor vdd, it can monitor any voltage lower than vdd. ct 4 3 reset delay time setting pin . connecting this pin to vdd through a 40 k to 200 k resistor or leaving it open results in fixed reset delay times. connecting this pin to a ground referenced capacitor ( 100 pf) gives a user?programmable reset delay time. see the setting reset delay time section for more information. mr 3 4 manual reset input , mr low asserts reset . mr is internally tied to vdd by a 90 k pull?up resistor. reset 1 6 reset output , is an active low open drain n?channel mosfet output, it is driven to a low impedance state when reset is asserted (either the sense input is lower than the threshold voltage (v it ) or the mr pin is set to a logic low). reset will keep low (asserted) for the reset delay time after both sense is above v it and mr is set to a logic high. a pull?up resistor from 10k to 1m should be used on this pin. see figure 5 for behavior of reset depends on vdd, sense and mr conditions. gnd 2 5 ground terminal . should be connected to pcb ground reference exp pad ? exposed pad exposed pad , under wdfn6 package, connect it to ground plane for better thermal dissipation.
ncp308, ncv308 www. onsemi.com 3 td tp2 0.0 v td tp1 td sense uncertain state figure 5. timing diagram showing mr and sense reset timing reset mr v dd(min) v it + v hys v it 0.7 v dd 0.3 v dd v dd table 2. truth table mr sense > v it reset l n l l y l h n l h y h
ncp308, ncv308 www. onsemi.com 4 table 3. maximum ratings rating symbol value unit input voltage range, v dd v dd ?0.3 to + 6.0 v ct voltage range v ct , reset , mr current through ct pin i ct ?0.3 to v dd +0.3 6.0 10 v ma sense pin voltage ?0.3 to + 8.0 v reset pin current 5 ma thermal resistance junction?to?air tsop?6 wdfn6 r ja 305 220 c/w human body model (hbm) esd rating (note 1) esd hbm 2000 v machine model (mm) esd rating (note 1) esd mm 100 v charged device model (cdm) esd rating (note 1) esd cdm 500 v latch up current: (note 2) all pins, except digital pins digital pins (mr ) i lu 100 10 ma storage temperature range t stg ?65 to + 150 c maximum junction temperature t j ?40 to +150 c moisture sensitivity (note 3) msl level 1 stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device function ality should not be assumed, damage may occur and reliability may be affected. 1. this device series contains esd protection and passes the following tests: human body model (hbm) +/?2.0 kv per jedec standard: jesd22?a114 machine model (mm) +/?100 v per jedec standard: jesd22?a115 charged device model (cdm) 500 v per jedec standard: jesd22?c101. 2. latch up current per jedec standard: jesd78 class ii. 3. moisture sensitivity level (msl): 1 per ipc/jedec standard: j?std?020a.
ncp308, ncv308 www. onsemi.com 5 table 4. electrical characteristics 1.6 v v dd 5.5 v, r pullup = 100 k , c lreset = 50 pf, over operating temperature range (t j = ?40 c to +125 c), unless otherwise specified. typical values are at t j = +25 c. symbol parameter conditions min typ max unit v dd supply voltage range ?40 c < t j < +125 c 1.6 5.5 v v dd (min) minimum v dd guaranteed reset output valid (note 4) 0.5 0.8 v i dd supply current (current into vdd pin) v dd = 3.3v, reset not asserted mr , reset , ct open 1.6 5.0 a v dd = 5.5v, reset not asserted mr , reset , ct open 1.6 6.0 v ol low?level output voltage of reset 1.3v v dd < 1.6v, i ol = 0.4 ma 0.3 v 1.6v v dd 5.5v, i ol = 1.0 ma 0.4 v it % negative going sense threshold voltage accuracy ?1.75 0.75 +1.75 % t j = +25 c ?0.31 ? 0.31 ?20 c < t j < +85 c ?1.0 0.5 +1.0 v hys hysteresis on v it 1.6v v dd 4.2v 1.0 3.0 %v it 4.2v v dd 5.5v 1.75 3.75 r mr mr internal pull?up resistance 90 k i sense input current at sense pin ncp308xxadj v sense = v it 10 na fixed versions v sense = 5.5 v 110 i oh reset leakage current v reset = 5.5 v, reset not asserted 300 na c in input capacitance, any pin ct pin v in = 0 v to v dd 5 pf other pins v in = 0 v to 5.5 v 5 v il mr logic low input 0 0.3 v dd v v ih mr logic high input 0.7 v dd v dd v tw input pulse width to assert reset sense v ih = 1.05 v it , v il = 0.95 v it 20 s mr v ih = 0.7 v dd , v il = 0.3 v dd 150 t d reset delay time c t = open c t = v dd c t = 100 pf c t = 180 nf (guaranteed by design and characterization) 20 300 1.25 1200 ms t p1 propagation delay from mr mr to reset v ih = 0.7 v dd , v il = 0.3 v dd 150 ns t p2 propagation delay from sense sense to reset v ih = 1.05 v it , v il = 0.95 v it 20 s 4. the lowest supply voltage (v dd ) at which reset becomes active. 5. ncp308xx: xx = mt (wdfn6 package) or sn (tsop?6 package).
ncp308, ncv308 www. onsemi.com 6 typical operating characteristics figure 6. supply current vs. input voltage v dd (v) 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 i dd ( a) +125 c +25 c +85 c ?40 c 0 1 10 100 1000 10000 0.1 1.0 10.0 100.0 1000 .0 figure 7. reset timeout period vs. ct (nf) (ms) +25 c ?40 c +125 c +85 c figure 8. normalized reset timeout period vs. temperature temperature ( c) ?50 20 normalized reset timeout period (%) 15 10 5.0 0 ?5.0 ?10 ?30 ?10 10 30 50 70 90 110 130 100 0 figure 9. maximum transient duration at sense vs. sense threshold overdrive voltage overdrive (%v it ) transient duration below v it ( s) 10 1 0.1 510152025 50 30 35 45 40 figure 10. normalized sense threshold voltage (v it ) vs. temperature temperature ( c) ?50 3.0 normalized v it (%) ?30 ?10 10 30 50 70 90 110 130 2.5 2.0 1.5 1.0 0.5 0 ?0.5 ?1.0 ?1.5 ?2.0 ?2.5 ?3.0 0.0 0.1 0.2 0.3 0.4 0.5 0.0 0.5 1.0 1.5 2.0 figure 11. low?level reset voltage vs. reset current reset current (ma) v ol low?level reset voltage (v) v dd = 1.6 v v dd = 3.3 v v dd = 5.5 v
ncp308, ncv308 www. onsemi.com 7 detailed description the ncp308 microprocessor supervisory product family is designed to assert a reset signal when either the sense pin voltage drops below v it or the manual reset input (mr ) is driven low. the reset output remains asserted for a programmable delay time after both mr and sense voltages return above the respective thresholds. a broad range of voltage threshold and reset delay time options are available, allowing ncp308 series to be used in a wide range of applications. reset threshold voltages can be factory?set from 0.82 v to 3.3 v or from 4.4 v to 5.0 v, while the ncp308xxadj can be used for any voltage above 0.405 v using an external resistor divider. flexible delay time can be easily got with ct pin according to table 5: table 5. delay time setting table ct pin configuration delay time (td) ct = vdd 300 ms (fixed) ct = open 20 ms (fixed) connecting a capacitor be- tween pin ct and gnd (capacitor ct value > 100 pf) 1.25 ms ~ 10 s, depends on capacitor value (refer to the setting reset delay time section) output the reset output is typically connected to the reset control pin of a microprocessor. for open?drain output versions, a pull?up resistor must be used to hold this line high when reset is not asserted. the reset output is active once v dd is over v dd (min), this voltage is much lower than most microprocessors? functional voltage range. reset remains high as long as sense is above its threshold (v it ) and the manual reset input (mr ) is logic high. if either sense falls below v it or mr is driven low, reset is asserted. once mr is again logic high and sense is above (v it + v hys ), the reset pin goes to a high impedance state after delay time (td). the open?drain structure of reset is capable to allow the reset signal for the microprocessor to have a voltage higher than v dd (up to 5.5 v). the pull?up resistor should be no smaller than 10 k as a result of the finite impedance of the reset line. sense input the sense input should be connected to the monitored voltage directly. if the voltage on this pin drops below v it , then reset is asserted. the comparator has a built?in hysteresis to prevent erratic reset operation. it is good practice to put a 1 nf to 10 nf bypass capacitor on the sense input to reduce its sensitivity to transients and layout parasitic. the ncp308xxadj can be used to monitor any voltage rail down to 0.405 v by the circuit shown in figure 12. the new v it ? can be derived from resistor divider network of r1 and r2 by: v it r1 r2 1 v it (eq. 1) vin vdd (optional) rpullup sense ct gnd vdd ct r1 r2 1 nf (optional) ncp308xxadj figure 12. using ncp308xxadj to monitor a user?defined threshold voltage mr reset mr manual reset input (mr ) the manual reset input (mr ) allows a processor or other logic circuits to initiate a reset. a logic low on mr causes reset to assert. after mr returns to a logic high and sense is above its reset threshold, reset is de?asserted after the delay time set by ct pin. mr is internally tied to v dd by a 90 k resistor so this pin can be left unconnected if mr will not be used. figure 13 shows how mr can be used to monitor multiple system voltages (e.g. i/o supply voltage of some dsp/processors should be setup before core voltage, and dsp/processor can only start after both i/o and core voltages setup).
ncp308, ncv308 www. onsemi.com 8 ncp308xx330 sense ct gnd vdd ncp308xx120 sense ct gnd vdd 3.3 v dsp/ reset vio 1.2 v vcore figure 13. using mr to monitor multiple system voltages mr reset processor mr reset setting reset delay time the ncp308 has three options for setting the reset delay time as shown in t able 5. figure 14 shows the configuration for a fixed 300 ms typical delay time by tying ct to v dd ; a resistor from 40 k to 200 k must be used. figure 15 shows a fixed 20 ms delay time by leaving the ct pin unconnected. figure 16 shows a user?defined program time between 1.25 ms and 10 s by connecting a capacitor between ct pin and ground. 3.3 v mr rpullup sense ct gnd vdd 50k figure 14. delay time fixed to 300 ms when ct connected to vdd by resistor mr reset 3.3v mr rpullup sense ct gnd vdd figure 15. delay time fixed to 20 ms when ct is open mr reset 3.3 v mr rpullup sense ct gnd vdd ct figure 16. delay time set by capacitor mr reset the capacitor ct should be 100 pf for ncp308 to recognize that the capacitor is present. the capacitor value for a given delay time can be calculated using the following equation:
ncp308, ncv308 www. onsemi.com 9 ct(nf) td(s) 0.5 10 ?3 (s) 175 (eq. 2) parasitic capacitances of ct pin should be considered to avoid reset delay time deviation or error. immunity to sense pin voltage transients ncp308 is relatively immune to short negative transients on sense pin. sensitivity to transients is dependent on threshold overdrive, as shown in the maximum transient duration at sense vs. sense threshold overdrive voltage graph (figure 9) in typical operating characteristics section. ordering information device status (note 6) threshold voltage (v it ) nominal monitored voltage marking package shipping ? ncp308snadjt1g active 0.405 v adjustable version adj tsop?6 (pb?free) 3000 / tape & reel ncv308snadjt1g* active 0.405 v vdj ncp308sn090t1g active 0.84 v 0.9 v 090 ncp308sn120t1g active 1.12 v 1.2 v 120 ncp308sn125t1g active 1.16 v 1.25 v 125 ncp308sn150t1g active 1.40 v 1.5 v 150 ncp308sn180t1g active 1.67 v 1.8 v 180 ncp308sn190t1g active 1.77 v 1.9 v 190 ncp308sn250t1g active 2.33 v 2.5 v 250 ncp308sn280t1g active 2.61 v 2.8 v 280 ncp308sn300t1g active 2.79 v 3.0 v 300 ncp308sn330t1g active 3.07 v 3.3 v 330 NCV308SN330T1G* active 3.07 v 3.3 v 33a ncp308sn500t1g active 4.65 v 5.0 v 500 ncp308mtadjtbg active 0.405 v adjustable version aa wdfn6 (pb?free) ncp308mt090tbg active 0.84 v 0.9 v ac ncp308mt120tbg active 1.12 v 1.2 v ad ncp308mt125tbg active 1.16 v 1.25 v ae ncp308mt150tbg active 1.40 v 1.5 v af ncp308mt180tbg active 1.67 v 1.8 v ag ncp308mt190tbg active 1.77 v 1.9 v ah ncp308mt250tbg active 2.33 v 2.5 v aj ncp308mt280tbg active 2.61 v 2.8 v ak ncp308mt300tbg active 2.79 v 3.0 v al ncp308mt330tbg active 3.07 v 3.3 v am ncp308mt500tbg active 4.65 v 5.0 v an ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d. *ncv prefix for automotive and other applications requiring unique site and control change requirements; aec?q100 qualified and ppap capable. 6. the marketing status are defined as below: active: products in production and recommended for new designs; under request: device has been announced but is not in production. samples may or may not be available.
ncp308, ncv308 www. onsemi.com 10 package dimensions case 318g?02 issue u 23 4 5 6 d 1 e b e1 a1 a 0.05 notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. maximum lead thickness includes lead finish. minimum lead thickness is the minimum thickness of base material. 4. dimensions d and e1 do not include mold flash, protrusions, or gate burrs. mold flash, protrusions, or gate burrs shall not exceed 0.15 per side. dimensions d and e1 are determined at datum h. 5. pin one indicator must be located in the indicated zone. c *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* dim a min nom max millimeters 0.90 1.00 1.10 a1 0.01 0.06 0.10 b 0.25 0.38 0.50 c 0.10 0.18 0.26 d 2.90 3.00 3.10 e 2.50 2.75 3.00 e 0.85 0.95 1.05 l 0.20 0.40 0.60 0.25 bsc l2 ? 0 1 0 1.30 1.50 1.70 e1 e recommended note 5 l c m h l2 seating plane gauge plane detail z detail z 0.60 6x 3.20 0.95 6x 0.95 pitch dimensions: millimeters m
ncp308, ncv308 www. onsemi.com 11 package dimensions notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b applies to plated terminal and is measured between 0.15 and 0.25 mm from the terminal tip. 4. coplanarity applies to the exposed pad as well as the terminals. seating plane d e 0.10 c a3 a a1 0.10 c wdfn6 2x2, 0.65p case 511br issue o dim a min max millimeters 0.70 0.80 a1 0.00 0.05 a3 0.20 ref b 0.25 0.35 d 2.00 bsc d2 1.50 1.70 0.90 1.10 e 2.00 bsc e2 e 0.65 bsc 0.20 0.40 l pin one reference 0.05 c 0.05 c note 4 a 0.10 c note 3 l e d2 e2 b b 3 6 6x 1 4 0.05 c mounting footprint* bottom view recommended dimensions: millimeters l1 detail a l alternate constructions l ??? --- 0.15 l1 6x 0.45 2.30 1.12 1.72 0.65 pitch 6x 0.40 1 package outline 6x m m *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. on semiconductor and are registered trademarks of semiconductor co mponents industries, llc (scillc). scillc owns the rights to a numb er of patents, trademarks, copyrights, trade secrets, and other inte llectual property. a listing of scillc?s pr oduct/patent coverage may be accessed at ww w.onsemi.com/site/pdf/patent?marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/ or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typical s? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or a uthorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in whic h the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or us e scillc products for any such unintended or unauthorized appli cation, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unin tended or unauthorized use, even if such claim alleges that scil lc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyrig ht laws and is not for resale in any manner. p ublication ordering information n. american technical support : 800?282?9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81?3?5817?1050 ncp308/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loc al sales representative

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